搜索资源列表
pipeline_add
- pipeline式累加器的verilog代码和testbench文件，已验证-pipeline type accumulator verilog testbench code and documents, verified
16Bit-Group-Ripple-Adder
- Verilog Testbench for 16Bit Group Ripple Adder
fpga
- 有关FPGA的好多资料的综合汇总，包括夏宇闻-Verilog经典教程，Verilog-testbench的写法，Altera+FPGA／CPLD设计高级篇，Altera+FPGA／CPLD设计基础篇等好几本书，超值-A comprehensive summary of a lot of information about FPGA, including Xia Wen-Verilog classic tutorial, Verilog-testbench writing, senior Alte
i2c_master
- verilog i2c master rtl+testbench 转自特权同学(verilog i2c master rtl+testbench)
i2c_slave
- Verilog i2c slave rtl + testbench 仿真ok(Verilog i2c slave rtl + testbench)
I2C_slaver_verison3.0
- I2C从机模块，包含testbench，平台是vivado,仿真测试通过。(I2C slave module, including testbench, the platform is vivado, simulation test passed.)
New folder
- clock div testbench design and frquency division
SEQ_DETECTOR
- 这是一个四位串行数据检测器，一共有三种模式可以选择：递增（检测连续四位递增序列），递减（检测连续四位递减序列）和不变（检测连续四位不变序列）。整个设计采用同步时钟，异步复位，用米利状态机，并配置好了仿真环境和仿真文件。(This is a four bit sequence detector, including three modes that can be selected: increment mode (detecting four consistency increment data)
anc dec
- encoder,decoder,testbench and run files
uygulama1
- verilog hdl, haladder testbench
uart
- 用Verilog实现FPGA的uart的串行通信功能，并附有testbench(The serial communication function of FPGA of UART is realized with Verilog, and Testbench is attached)
ADC_Data_Recv_Module
- 接收机测试输入信号， 生成正余弦波，采样率、频率、幅度、相位可调节 并将生成的数据进行输出 压缩包包括Verilog代码、testbench代码、word文档 matlab仿真代码(The receiver tests the input signal, Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted And output the generated da
Clock_Synchronization_Module
- 数字接收机中频部分数字时钟的设计 包括matlab仿真 verilog代码、 testbench代码 以及word设计文档(Design of medium frequency digital clock in digital receiver Including Matlab simulation Verilog, testbench code, and design documents)
float_adder
- 实现可调维度的浮点数加法运算，内涵各个子模块和testbench(Able to achieve the float numbers adding operation.)
frequency divider and testbench
- a frequency divider and test bench with simulation results
aes-master
- Verilog写的AES加密解密代码，带testbench。(AES encryption code written by Verilog with testbench.)
electrical lock
- 一个用Verilog写的电子锁工程，带testbench。(An electronic lock project written in Verilog with testbench.)
FP_adder
- 32 bit floating point adder with testbench
HDL_equation
- Verilog Program to implement the function f=x+yz and Testbench for all the possible inputs using For Loop
adder
- 实现了加法器功能，包含testbench(Implements the adder function)